1. Technical Field of the Invention
The present invention relates generally to testing integrated circuits and more particularly to allowing various points within an integrated circuit to be tested non-invasively irrespective of whether or not the integrated circuit is packaged.
2. Background Information
The ubiquitous presence of integrated circuits (ICs) in almost every electronic device is testament to their importance in today's society. ICs are generally manufactured in wafer form, where multiple ICs are manufactured in an array using photolithography techniques. FIG. 1 illustrates an exemplary wafer 20 having a frontside 20A and a backside 20B, where arrays of ICs are manufactured on the frontside 20A. Separating the ICs from each other may be accomplished by dicing the wafer along the orthogonal scribe lines. The ICs may be tested at various stages in the manufacturing process. For example, the ICs may be tested while they are in wafer form. Alternatively, the ICs may be tested after they are separated from each other but prior to being completely packaged. Also, the ICs may be tested after they have been packaged by accessing the various pins of the package.
One method of testing ICs consists of mechanical probing the completed IC on the wafer. Mechanical probing is accomplished by placing fine needles onto pads designed into the IC for this purpose. Due to performance constraints of the mechanical probing system several problems occur that limit detection of defective ICs. The first problem is with touching the pads. Repeated contact of the needles with the pads causes cracking of the materials that form the pad structure. The second problem is with the inductance of the mechanical probing system, which can be several orders of magnitude higher than other inductances of the IC. This high inductance limits the speed at which the IC can be tested.
Another method of testing the ICs includes micro-mechanical probing. Micro-mechanical probing is generally accomplished by using fine tipped mechanical probes to make physical contact with various points on the surface of the IC. Probing ICs in this manner can be problematic for several reasons. For example, IC technology trends indicate that the dimensions of ICs decrease with time, which results in smaller and smaller devices on the IC. Consequently, it can be difficult to locate a desired device on the IC using a micro-mechanical probe. Also, since the probe needles tend to be very small (on the order of 1 μm or smaller) they may be easily bent. In addition, when large volumes of ICs are being tested in this manner, physically attaching and detaching the micro-mechanical probes to each IC may consume too much time. Furthermore, if the IC has been packaged, portions of the package may need to be removed to gain access, and if the is IC is packaged in a “flip-chip” package, physical access to desired points on the IC via micro-mechanical probes may not be possible.
Yet another testing method is to test in the IC after final packaging. In this case the packaged IC is connected to the test apparatus through the connections of the package. At speed testing is generally not an issue in this test methodology as the connections emulate the actual operation of the IC in the customer application. In the case of testing packaged IC the cost of testing is one of the most important issues. This cost-effective technique that can permit at speed testing is desirable.
Recent testing trends involving optical techniques have proven useful in post mortem analysis of defective ICs—i.e., failure analysis tests. One optical technique involves exposing an IC to a light source that may be in the infrared or visible wavelength region in order to perturb the state of individual circuit elements. Perturbing individual circuit elements on the IC in this manner allows defective circuit elements on the defective IC to be determined. For example, if it is believed that an individual transistor is defective, the state of this transistor may be perturbed by light to turn the transistor on and off. While the transistor is being turned on and off by the light source, the current in the transistor may be measured to ensure that the transistor consumes a predetermined amount of current while the transistor is on, and likewise consumes a negligible amount of current when the transistor is off. If the transistor does not consume the expected amount of current in either case it may be deemed defective and the root defect of the defective IC may be determined.
Another optical technique called Picosecond imaging circuit analysis (PICA) was recently developed by IBM and is described in “Picosecond imaging circuit analysis,” IBM J Res. Develop., Vol. 44, No. 4, July 2000. PICA techniques rely on a combination of physical phenomena that are present in modem digital circuits. Modern digital circuits include metal-oxide semiconductor transistors (MOSFETs), which typically operate in the saturation region of their current-voltage curves when “ON”. While in the saturation region, very high electric fields exist in the channel. Charge can-jers (i.e., electrons and holes) can quickly gain a significant amount of kinetic energy in such electric fields, and indeed, many “hot” carriers are generated in this manner when current flows through the channel. A variety of scattering and recombination mechanisms may strip the energy from “hot” carriers, and in so doing, may trigger the emission of a photon of light. The light is emitted over a wide range of frequencies, but the infrared band of the spectrum is particularly significant because silicon is relatively transparent there. As a result, transistors that carry current emit infrared light, and optical images of an IC may be made based on this light emission. Further, multiple optical images may be taken while an IC is operating, and when looking at the images consecutively with respect to time, a “movie” may be generated indicating which circuit elements are on at which times.
The PICA method may be used to root out defective circuit elements. For example, if a metal interconnect on an IC is blown causing a transistor to continually be in the saturation mode, then this transistor will emit light and will be more prominent in the PICA images. Consequently, failure analysis engineers may consult circuit schematics and perform additional testing to determine that the metal interconnect is the root cause of the problem. This example illustrates a downfall of the PICA method and other similar methods; that is, PICA simply conveys a “problem” spot on the IC, where this “problem” spot may be the result of the actual defect. Additionally, non-manufacturing IC defects may be difficult to detect using PICA. For example, if a critical circuit block such as an arithmetic logic unit (ALU) is not performing mathematical operations correctly due to a programming error, then PICA methods may be less effective because the error may not manifest itself as a transistor conducting current and therefore may be more difficult to notice on a PICA image. Accordingly, methods and apparatuses are needed that allow more sophisticated non-invasive testing of ICs to be accomplished.